On 1/22/19 12:22 AM, Richard Henderson wrote:
On 1/21/19 1:10 AM, Bastian Koppelmann wrote:
On 1/20/19 2:43 AM, Richard Henderson wrote:
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.ad...@hni.uni-paderborn.de>
---
v3 -> v4:
- refactor tcg_gen_set_cond_tl(TCG_COND_LT,..) into gen_slt function
and reuse gen_arith(..., &gen_slt) for all trans_slt functions.
- Add missing sign extension to trans_srlw/sllw
- Made rs2 == 0 a special case of srlw/sllw
Why? It's not like it is a likely case, and it works without.
Because you suggested it :) (see https://patchwork.kernel.org/patch/10662699/).
Maybe I misunderstood your comment. If you like I can remove it in the respin.
I meant the register indicated by rs2 containing the value 0,
which you have fixed with the extension.
I see. I remove it in the respin.
Cheers,
Bastian
