Update the stepping from 5 to 6, in order that
the Cascadelake-Server CPU model can support AVX512VNNI
and MSR based features exposed by ARCH_CAPABILITIES.
Signed-off-by: Tao Xu <tao3...@intel.com>
---
include/hw/i386/pc.h | 4 ++++
target/i386/cpu.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c7c0c944e8..95453968db 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -300,6 +300,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "intel-iommu",\
.property = "dma-drain",\
.value = "off",\
+ },{\
+ .driver = "Cascadelake-Server" "-" TYPE_X86_CPU,\
+ .property = "stepping",\
+ .value = "5",\
},
#define PC_COMPAT_3_0 \
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 677a3bd5fb..09706ad51a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2466,7 +2466,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
- .stepping = 5,
+ .stepping = 6,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
--
2.17.1
