On 12/11/18 2:46 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at 08:46:05PM +0100, Cédric Le Goater wrote:
>> Currently, the interrupt presenter of the vCPU is set at realize
>> time. Setting it at reset will become useful when the new machine
>> supporting both interrupt modes is introduced. In this machine, the
>> interrupt mode is chosen at CAS time and activated after a reset.
>>
>> Signed-off-by: Cédric Le Goater <c...@kaod.org>
>
> Shouldn't this also remove the code which sets cpu->intc at realize
> time, in order to avoid confusion?
yes. Which also raises the question of the parenthood when a CPU is
hot-unplugged (spapr_unrealize_vcpu)
C.
>
>> ---
>> include/hw/ppc/spapr_cpu_core.h | 2 ++
>> hw/ppc/spapr_cpu_core.c | 26 ++++++++++++++++++++++++++
>> hw/ppc/spapr_irq.c | 12 ++++++++++++
>> 3 files changed, 40 insertions(+)
>>
>> diff --git a/include/hw/ppc/spapr_cpu_core.h
>> b/include/hw/ppc/spapr_cpu_core.h
>> index 9e2821e4b31f..fc8ea9021656 100644
>> --- a/include/hw/ppc/spapr_cpu_core.h
>> +++ b/include/hw/ppc/spapr_cpu_core.h
>> @@ -53,4 +53,6 @@ static inline sPAPRCPUState *spapr_cpu_state(PowerPCCPU
>> *cpu)
>> return (sPAPRCPUState *)cpu->machine_data;
>> }
>>
>> +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type);
>> +
>> #endif
>> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
>> index 1811cd48db90..529de0b6b9c8 100644
>> --- a/hw/ppc/spapr_cpu_core.c
>> +++ b/hw/ppc/spapr_cpu_core.c
>> @@ -398,3 +398,29 @@ static const TypeInfo spapr_cpu_core_type_infos[] = {
>> };
>>
>> DEFINE_TYPES(spapr_cpu_core_type_infos)
>> +
>> +typedef struct ForeachFindIntCArgs {
>> + const char *intc_type;
>> + Object *intc;
>> +} ForeachFindIntCArgs;
>> +
>> +static int spapr_cpu_core_find_intc(Object *child, void *opaque)
>> +{
>> + ForeachFindIntCArgs *args = opaque;
>> +
>> + if (object_dynamic_cast(child, args->intc_type)) {
>> + args->intc = child;
>> + }
>> +
>> + return args->intc != NULL;
>> +}
>> +
>> +void spapr_cpu_core_set_intc(PowerPCCPU *cpu, const char *intc_type)
>> +{
>> + ForeachFindIntCArgs args = { intc_type, NULL };
>> +
>> + object_child_foreach(OBJECT(cpu), spapr_cpu_core_find_intc, &args);
>> + g_assert(args.intc);
>> +
>> + cpu->intc = args.intc;
>> +}
>> diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c
>> index 7a0d4f529763..b423cee30e2c 100644
>> --- a/hw/ppc/spapr_irq.c
>> +++ b/hw/ppc/spapr_irq.c
>> @@ -12,6 +12,7 @@
>> #include "qemu/error-report.h"
>> #include "qapi/error.h"
>> #include "hw/ppc/spapr.h"
>> +#include "hw/ppc/spapr_cpu_core.h"
>> #include "hw/ppc/spapr_xive.h"
>> #include "hw/ppc/xics.h"
>> #include "sysemu/kvm.h"
>> @@ -211,6 +212,11 @@ static int spapr_irq_post_load_xics(sPAPRMachineState
>> *spapr, int version_id)
>>
>> static void spapr_irq_reset_xics(sPAPRMachineState *spapr, Error **errp)
>> {
>> + CPUState *cs;
>> +
>> + CPU_FOREACH(cs) {
>> + spapr_cpu_core_set_intc(POWERPC_CPU(cs), spapr->icp_type);
>> + }
>> }
>>
>> #define SPAPR_IRQ_XICS_NR_IRQS 0x1000
>> @@ -341,6 +347,12 @@ static int spapr_irq_post_load_xive(sPAPRMachineState
>> *spapr, int version_id)
>>
>> static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
>> {
>> + CPUState *cs;
>> +
>> + CPU_FOREACH(cs) {
>> + spapr_cpu_core_set_intc(POWERPC_CPU(cs), TYPE_XIVE_TCTX);
>> + }
>> +
>> /*
>> * Set the OS CAM line of the cpu interrupt thread context. Needs
>> * to come after the XiveTCTX reset handlers.
>
