On 05/12/18 16:13, Li Qiang wrote: > Here my question when the piix3’s PIRQx route control registers is set > and by who? > > I mean when this ‘‘piix3->dev.config[PIIX_PIRQC + pin];’’ is set? > > Once I think this is set by seabios.
Hi, it's set by the operating system via ACPI. Search for define_link in SeaBIOS's src/fw/acpi-dsdt.dsl, it refers to fields called PRQ0-PRQ3 which in turn are defined like this: /* PIIX PCI to ISA irq remapping */ OperationRegion(P40C, PCI_Config, 0x60, 0x04) ... Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) { PRQ0, 8, PRQ1, 8, PRQ2, 8, PRQ3, 8 } Current QEMU doesn't use anymore the SeaBIOS copy of the DSDT, but the same thing can be found in build_piix4_isa_bridge and build_piix4_pci0_int, in hw/i386/acpi-build.c. > But seems it is not as this function is called in vfio_realize, the > guest dones’t begin. vfio also calls it (from vfio_intx_update) every time the routing registers are updated. The ISA bridge calls pci_bus_fire_intx_routing_notifier, and then that function calls vfio_intx_update, because it was registered with pci_device_set_intx_routing_notifier. Thanks, Paolo