On 2 November 2018 at 13:41, Richard Henderson
<richard.hender...@linaro.org> wrote:
> The bulk of the work here, beyond base HPD, is defining the TTBCR2 register.
> In addition we must check TTBCR.T2E, which is not present (RES0) for AArch64.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/cpu.h | 8 ++++++++
> target/arm/cpu.c | 4 ++++
> target/arm/helper.c | 37 +++++++++++++++++++++++++++++--------
> 3 files changed, 41 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index f12a6afddc..a253cdebde 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1517,6 +1517,14 @@ FIELD(ID_ISAR6, FHM, 8, 4)
> FIELD(ID_ISAR6, SB, 12, 4)
> FIELD(ID_ISAR6, SPECRES, 16, 4)
>
> +FIELD(ID_MMFR4, SPECSEI, 0, 4)
> +FIELD(ID_MMFR4, AC2, 4, 4)
> +FIELD(ID_MMFR4, XNX, 8, 4)
> +FIELD(ID_MMFR4, CNP, 12, 4)
> +FIELD(ID_MMFR4, HPDS, 16, 4)
> +FIELD(ID_MMFR4, LSM, 20, 4)
> +FIELD(ID_MMFR4, CCIDX, 24, 4)
Why all caps for SpecSEI in this register, but honouring the
capitalization from the spec in the equivalent ID register
added in patch 1? ("FIELD(ID_AA64MMFR1, SpecSEI, 24, 4)")
I don't mind which, but we should pick a convention and stick
to it.
thanks
-- PMM
