On 10/31/18 1:19 PM, Bastian Koppelmann wrote: > this splits the 64-bit only instructions into its own decode file such > that we generate the decoder for these instructions only for the RISC-V > 64 bit target. > > Signed-off-by: Bastian Koppelmann <kbast...@mail.uni-paderborn.de> > Signed-off-by: Peer Adelt <peer.ad...@hni.uni-paderborn.de> > --- > target/riscv/Makefile.objs | 8 +++++--- > target/riscv/insn64.decode | 25 +++++++++++++++++++++++++ > target/riscv/insn_trans/trans_rvi.inc.c | 20 ++++++++++++++++++++ > target/riscv/translate.c | 7 ------- > 4 files changed, 50 insertions(+), 10 deletions(-) > create mode 100644 target/riscv/insn64.decode
I did suggest using insn32-64.decode, so that insn64.decode is available for an actual 64-bit instruction word, which is mentioned in the "Extensions" section of the ISA manual. However, Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
