From: Guenter Roeck <li...@roeck-us.net>
QEMU already supports pl330. Instantiate it for smdkc210.
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
/ {
soc: soc {
amba {
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
};
};
Signed-off-by: Guenter Roeck <li...@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <phi...@redhat.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
[PMD: Do not set default qdev properties, create the controllers in the SoC
rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <phi...@redhat.com>
---
Another intent to salvage previous work from Guenter Roeck:
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06302.html
Since v2: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06459.html
- rename init -> create
- create controllers in SoC rather than the board (Peter Maydell)
- add Linux dtsi in commit message
Since v1: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06335.html
- Do not factor out pl330_init, which resulted in buggy v1, see:
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg06448.html
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 827318a003..cd27b9387c 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -96,6 +96,11 @@
/* EHCI */
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
+
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
0x09, 0x00, 0x00, 0x00 };
@@ -160,6 +165,19 @@ static uint64_t exynos4210_calc_affinity(int cpu)
return (0x9 << ARM_AFF1_SHIFT) | cpu;
}
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+ SysBusDevice *busdev;
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, "pl330");
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
+ qdev_init_nofail(dev);
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, base);
+ sysbus_connect_irq(busdev, 0, irq);
+}
+
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
{
Exynos4210State *s = g_new(Exynos4210State, 1);
@@ -410,5 +428,13 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
s->irq_table[exynos4210_get_irq(28, 3)]);
+ /*** DMA controllers ***/
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
return s;
}
--
2.17.2
