Currently this holder is limited to at most 32 flags on
a 32-bit architecture, which lets an unique bit available
for another 'chip specific instructions' flag.
Relax this limit using a 64-bit integer.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/cpu.h | 2 +-
target/mips/internal.h | 2 +-
target/mips/translate.c | 8 ++++----
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d191c..f2a5031fd2 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -614,7 +614,7 @@ struct CPUMIPSState {
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
- int insn_flags; /* Supported instruction set */
+ uint64_t insn_flags; /* Supported instruction set */
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f8e6..bfe83ee613 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -59,7 +59,7 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask;
- int insn_flags;
+ uint64_t insn_flags;
enum mips_mmu_types mmu_type;
};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5a5021fe36..2aa8dd884d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1447,7 +1447,7 @@ typedef struct DisasContext {
target_ulong saved_pc;
target_ulong page_start;
uint32_t opcode;
- int insn_flags;
+ uint64_t insn_flags;
int32_t CP0_Config1;
int32_t CP0_Config3;
int32_t CP0_Config5;
@@ -1870,7 +1870,7 @@ static inline void check_dspr2(DisasContext *ctx)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(DisasContext *ctx, int flags)
+static inline void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -1880,7 +1880,7 @@ static inline void check_insn(DisasContext *ctx, int
flags)
/* This code generates a "reserved instruction" exception if the
CPU has corresponding flag set which indicates that the instruction
has been removed. */
-static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
+static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
generate_exception_end(ctx, EXCP_RI);
@@ -1895,7 +1895,7 @@ static inline void check_insn_opc_removed(DisasContext
*ctx, int flags)
* A reserved instruction exception is generated for flagged CPUs if
* QEMU runs in system mode.
*/
-static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
+static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
{
#ifndef CONFIG_USER_ONLY
check_insn_opc_removed(ctx, flags);
--
2.19.0
