On Sun, 30 Sep 2018, Philippe Mathieu-Daudé wrote:
> >> I'd use:
> >>
> >> MIPS_INVAL("mul/div Toshiba");
> >
> > But just like `gen_mul_vr54xx' this function doesn't handle division!
>
> Per the commit message, I understood this function would eventually
> handle "the R5900 specific pipeline 1 instruction variants MULT1,
> MULTU1, DIV1, DIVU1, ..."
Toshiba division instructions do not support the extra operand and always
return their result in the MD accumulator only. The same applies to the
pipeline 1 instruction variants, so I've been thinking that a different
handler would better be used for DIV1 and DIVU1. But maybe we can fold it
together after all and just force `rd' to be 0 at the call site for
DIV1/DIVU1.
I'm not sure at this point which approach would be most beneficial, but
as it stands the function does not handle division operations. If it
starts in the future, then we can rename/update it accordingly.
Note that while the R5900 (shouldn't that be called TX59 actually?) or
TX79 do not implement DMULT or DMULTU, the Tx49 does and they do support
the extra `rd' operand there[1]. Still no DMADD or DMADDU though.
References:
[1] "64-Bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture",
Rev 1.0, Toshiba Corporation, September 2004, Table 5-8 "Extensions to
the ISA: Multiply and Divide Instructions", p. 5-7
Maciej
