On 9/15/18 10:43 AM, Fredrik Noring wrote: > CPU_R5900 is defined as CPU_MIPS3 but it has the MIPS IV instructions > MOVN, MOVZ and PREF as well. > > Signed-off-by: Fredrik Noring <nor...@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> > --- > target/mips/translate.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/target/mips/translate.c b/target/mips/translate.c > index fb571e278e..c35be0053b 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -22402,7 +22402,7 @@ static void decode_opc_special_legacy(CPUMIPSState > *env, DisasContext *ctx) > case OPC_MOVN: /* Conditional move */ > case OPC_MOVZ: > check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | > - INSN_LOONGSON2E | INSN_LOONGSON2F); > + INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900); > gen_cond_move(ctx, op1, rd, rs, rt); > break; > case OPC_MFHI: /* Move from HI/LO */ > @@ -24986,7 +24986,8 @@ static void decode_opc(CPUMIPSState *env, > DisasContext *ctx) > break; > case OPC_PREF: > check_insn_opc_removed(ctx, ISA_MIPS32R6); > - check_insn(ctx, ISA_MIPS4 | ISA_MIPS32); > + check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 | > + INSN_R5900); > /* Treat as NOP. */ > break; > >
