Peter,
On 9/12/18 11:52 AM, Peter Xu wrote:
On Tue, Sep 11, 2018 at 11:49:49AM -0500, Brijesh Singh wrote:
Now that amd-iommu support interrupt remapping, enable the GASup in IVRS
table and GASup in extended feature register to indicate that IOMMU
support guest virtual APIC mode.
Note that the GAMSup is set to zero to indicate that Guest Virtual
APIC does not support advanced interrupt features (i.e virtualized
interrupts using the guest virtual APIC).
See Table 21 from IOMMU spec for interrupt virtualization controls
IOMMU spec: https://support.amd.com/TechDocs/48882_IOMMU.pdf
Cc: "Michael S. Tsirkin" <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: Richard Henderson <[email protected]>
Cc: Eduardo Habkost <[email protected]>
Cc: Marcel Apfelbaum <[email protected]>
Cc: Tom Lendacky <[email protected]>
Cc: Suravee Suthikulpanit <[email protected]>
Signed-off-by: Brijesh Singh <[email protected]>
---
hw/i386/acpi-build.c | 3 ++-
hw/i386/amd_iommu.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5c2c638..1cbc8ba 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2565,7 +2565,8 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linker)
build_append_int_noprefix(table_data,
(48UL << 30) | /* HATS */
(48UL << 28) | /* GATS */
- (1UL << 2), /* GTSup */
+ (1UL << 2) | /* GTSup */
+ (1UL << 6), /* GASup */
Sorry if I misunderstood - is this for nested?
I'm a bit confused here... IIUC in your previous patches you didn't
really implement guest_mode==1 case in IRTEs. So if you have this set
then the guest should be able to setup IRTEs with guest_mode==1? How
did it work?
Thanks,
The naming of these bits are confusing. Please allow me to help explain.
There are two capability bits:
* GASup : This is to allow 128-bit IRTE when GAEn is set.
* GAMSup : This is for Guest Virtual APIC mode support,
which is not currently supported in vIOMMU.
The commit message in patch 5 is incorrect.
Here, we set GASup in order to allow 128-bit IRTE support,
which is needed for some of future AMD IOMMU features.
Thanks,
Suravee
