On Tue, Sep 4, 2018 at 4:14 PM, Alistair Francis <alistair.fran...@wdc.com> wrote: > The following changes since commit 19b599f7664b2ebfd0f405fb79c14dd241557452: > > Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2018-08-27-v2' > into staging (2018-08-27 16:44:20 +0100) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-pullreq-20180904 > > for you to fetch changes up to 3b18c3fa870f11b8a1841bb7537e5bc11100160c: > > riscv: remove define cpu_init() (2018-09-04 13:24:39 -0700)
Disregard this, I have sent a v2. Alistair > > ---------------------------------------------------------------- > A misc collection of RISC-V related patches for 3.1. > > ---------------------------------------------------------------- > Alistair Francis (2): > hw/riscv/virtio: Set the soc device tree node as a simple-bus > hw/riscv/spike: Set the soc device tree node as a simple-bus > > Emilio G. Cota (2): > target/riscv: optimize indirect branches > target/riscv: call gen_goto_tb on DISAS_TOO_MANY > > Igor Mammedov (1): > riscv: remove define cpu_init() > > Michael Clark (4): > RISC-V: Update address bits to support sv39 and sv48 > RISC-V: Improve page table walker spec compliance > RISC-V: Use atomic_cmpxchg to update PLIC bitmaps > RISC-V: Simplify riscv_cpu_local_irqs_pending > > hw/riscv/sifive_plic.c | 49 ++++++++++----------- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 2 +- > include/hw/riscv/sifive_plic.h | 1 - > target/riscv/cpu.h | 9 ++-- > target/riscv/cpu_bits.h | 2 - > target/riscv/helper.c | 98 > ++++++++++++++++++++++++------------------ > target/riscv/translate.c | 9 +--- > 8 files changed, 87 insertions(+), 85 deletions(-) >
