> From: Craig Janeczek <jancr...@amazon.com>
> Sent: Tuesday, August 28, 2018 3:00 PM
> To: qemu-devel@nongnu.org
> Cc: Aleksandar Markovic; aurel...@aurel32.net; Craig Janeczek
> Subject: [PATCH v3 1/8] target/mips: Introduce MXU registers
>
> Define and initialize the 16 MXU registers.
>
> Signed-off-by: Craig Janeczek <jancr...@amazon.com>
> ---
> v1
> - NA
> v2
> - NA
> v3
> - Initial patch, split out from prior first patch
>
> target/mips/cpu.h | 1 +
> target/mips/translate.c | 16 ++++++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 009202cf64..4b2948a2c8 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -170,6 +170,7 @@ struct TCState {
> MSACSR_FS_MASK)
>
> float_status msa_fp_status;
> + target_ulong mxu_gpr[16];
> };
>
Where is the definition of MXU control register (MXU_CR)?
This may be placed in a separate patch, but must be includes in the series.
> typedef struct CPUMIPSState CPUMIPSState;
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index bdd880bb77..416488b383 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1398,6 +1398,9 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31;
> static TCGv_i64 fpu_f64[32];
> static TCGv_i64 msa_wr_d[64];
>
> +/* MXU registers */
> +static TCGv mxu_gpr[16];
> +
> #include "exec/gen-icount.h"
>
> #define gen_helper_0e0i(name, arg) do { \
> @@ -1517,6 +1520,13 @@ static const char * const msaregnames[] = {
> "w30.d0", "w30.d1", "w31.d0", "w31.d1",
> };
>
> +static const char * const mxuregnames[] = {
> + "XR1", "XR2", "XR3", "XR4", "XR5",
> + "XR6", "XR7", "XR8", "XR9", "XR10",
> + "XR11", "XR12", "XR13", "XR14", "XR15",
> + "XR16",
> +};
Better alignment:
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "XR16",
> +
> #define LOG_DISAS(...)
> \
> do {
> \
> if (MIPS_DEBUG_DISAS) {
> \
> @@ -20742,6 +20752,12 @@ void mips_tcg_init(void)
> fpu_fcr31 = tcg_global_mem_new_i32(cpu_env,
> offsetof(CPUMIPSState,
> active_fpu.fcr31),
> "fcr31");
> +
> + for (i = 0; i < 16; i++)
> + mxu_gpr[i] = tcg_global_mem_new(cpu_env,
> + offsetof(CPUMIPSState,
> + active_tc.mxu_gpr[i]),
> + mxuregnames[i]);
The body of the for loop must be enclosed in { and } (QEMU code style
guidelines).
Before sending patches, it is obligatory to run scripts/checkpatch.pl
<path-to-your-patches> - this (missing braces) will be reported by this script.
> }
>
> #include "translate_init.inc.c"
>
