From: Dimitrije Nikolic <dniko...@wavecomp.com> Amend regular MIPS' cpu_loop.c to include nanoMIPS support.
Signed-off-by: Aleksandar Rikalo <arik...@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com> Signed-off-by: Stefan Markovic <smarko...@wavecomp.com> --- linux-user/mips/cpu_loop.c | 8 +++++++- linux-user/nanomips/cpu_loop.c | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 linux-user/nanomips/cpu_loop.c diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index c9c20cf..ada5a79 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -546,7 +546,7 @@ void cpu_loop(CPUMIPSState *env) arg5, arg6, arg7, arg8); } done_syscall: -# else +# else /* N32/N64 and P32 */ ret = do_syscall(env, env->active_tc.gpr[2], env->active_tc.gpr[4], env->active_tc.gpr[5], env->active_tc.gpr[6], env->active_tc.gpr[7], @@ -562,6 +562,7 @@ done_syscall: Avoid clobbering register state. */ break; } +#if !defined(TARGET_ABI_MIPSP32) if ((abi_ulong)ret >= (abi_ulong)-1133) { env->active_tc.gpr[7] = 1; /* error flag */ ret = -ret; @@ -569,6 +570,9 @@ done_syscall: env->active_tc.gpr[7] = 0; /* error flag */ } env->active_tc.gpr[2] = ret; +#else + env->active_tc.gpr[4] = ret; +#endif break; case EXCP_TLBL: case EXCP_TLBS: @@ -714,6 +718,8 @@ done_syscall: } else { code = ((trap_instr >> 6) & ((1 << 10) - 1)); } + } else if (env->insn_flags & ISA_NANOMIPS32) { + code = ((trap_instr >> 11) & ((1 << 5) - 1)); } if (do_break(env, &info, code) != 0) { diff --git a/linux-user/nanomips/cpu_loop.c b/linux-user/nanomips/cpu_loop.c new file mode 100644 index 0000000..da4949a --- /dev/null +++ b/linux-user/nanomips/cpu_loop.c @@ -0,0 +1 @@ +#include "../mips/cpu_loop.c" -- 2.7.4