On 15 August 2018 at 15:39, Philippe Mathieu-Daudé <f4...@amsat.org> wrote:
> On 08/09/2018 10:01 AM, Peter Maydell wrote:
>> diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c
>> index a7aacad74f0..8f92550392b 100644
>> --- a/hw/dma/pl080.c
>> +++ b/hw/dma/pl080.c
>> @@ -229,7 +229,7 @@ static uint64_t pl080_read(void *opaque, hwaddr offset,
>> i = (offset & 0xe0) >> 5;
>> if (i >= s->nchannels)
>> goto bad_offset;
>> - switch (offset >> 2) {
>> + switch ((offset >> 2) & 7) {
>
> So only the first channel ever worked...
Not even that -- the per-channel registers are in the
0x100..0x200 region, so channel 0's registers start at 0x100.
> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
thanks
-- PMM
