Implement VA->PA translations by cp15-c7 that went through unchanged
previously.
Signed-off-by: Adam Lackorzynski <a...@os.inf.tu-dresden.de>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c9febfa..603574b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -126,6 +126,7 @@ typedef struct CPUARMState {
uint32_t c6_region[8]; /* MPU base/size registers. */
uint32_t c6_insn; /* Fault address registers. */
uint32_t c6_data;
+ uint32_t c7_par; /* Translation result. */
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint32_t c13_fcse; /* FCSE PID. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7f63a28..32cc795 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1456,8 +1456,52 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn,
uint32_t val)
case 7: /* Cache control. */
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
- /* No cache, so nothing to do. */
- /* ??? MPCore has VA to PA translation functions. */
+ /* No cache, so nothing to do except VA->PA translations. */
+ if (arm_feature(env, ARM_FEATURE_V6)) {
+ switch (crm) {
+ case 4:
+ env->cp15.c7_par = val;
+ break;
+ case 8: {
+ uint32_t phys_addr;
+ target_ulong page_size;
+ int prot;
+ int ret, is_user;
+ int access_type;
+
+ switch (op2) {
+ case 0: /* priv read */
+ is_user = 0;
+ access_type = 0;
+ break;
+ case 1: /* priv write */
+ is_user = 0;
+ access_type = 1;
+ break;
+ case 2: /* user read */
+ is_user = 1;
+ access_type = 0;
+ break;
+ case 3: /* user write */
+ is_user = 1;
+ access_type = 1;
+ break;
+ default: /* 4-7 are only available with TZ */
+ goto bad_reg;
+ }
+ ret = get_phys_addr_v6(env, val, access_type, is_user,
+ &phys_addr, &prot, &page_size);
+ if (ret == 0) {
+ env->cp15.c7_par = phys_addr;
+ if (page_size > TARGET_PAGE_SIZE)
+ env->cp15.c7_par |= 1 << 1;
+ } else {
+ env->cp15.c7_par = ret | 1;
+ }
+ break;
+ }
+ }
+ }
break;
case 8: /* MMU TLB control. */
switch (op2) {
@@ -1789,6 +1833,9 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
}
}
case 7: /* Cache control. */
+ if (crm == 4 && op2 == 0) {
+ return env->cp15.c7_par;
+ }
/* FIXME: Should only clear Z flag if destination is r15. */
env->ZF = 0;
return 0;
--
1.7.2.3
Adam
--
Adam a...@os.inf.tu-dresden.de
Lackorzynski http://os.inf.tu-dresden.de/~adam/
