From: Stefan Markovic <smarko...@wavecomp.com>
Add emulation of MT ASE instructions for nanoMIPS.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
---
target/mips/translate.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9baacff..c09416b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16606,7 +16606,7 @@ static void gen_pool16c_nanomips_insn(DisasContext *ctx)
}
}
-static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
+static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
{
int rt = (ctx->opcode >> 21) & 0x1f;
int rs = (ctx->opcode >> 16) & 0x1f;
@@ -16779,6 +16779,87 @@ static void gen_pool32a0_nanomips_insn(DisasContext
*ctx)
tcg_temp_free(t0);
}
break;
+ case NM_D_E_MT_VPE:
+ {
+ uint8_t sc = (ctx->opcode >> 10) & 1;
+ TCGv t0 = tcg_temp_new();
+
+ switch (sc) {
+ case 0:
+ if (rs == 1) {
+ /* DMT */
+ check_insn(ctx, ASE_MT);
+ gen_helper_dmt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* DVPE */
+ check_insn(ctx, ASE_MT);
+ gen_helper_dvpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ case 1:
+ if (rs == 1) {
+ /* EMT */
+ check_insn(ctx, ASE_MT);
+ gen_helper_emt(t0);
+ gen_store_gpr(t0, rt);
+ } else if (rs == 0) {
+ /* EVPE */
+ check_insn(ctx, ASE_MT);
+ gen_helper_evpe(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ break;
+ }
+
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_FORK:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+ gen_helper_fork(t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case NM_MFTR:
+ case NM_MFHTR:
+ check_insn(ctx, ASE_MT);
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return;
+ }
+ gen_mftr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1,
+ (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1);
+ break;
+ case NM_MTTR:
+ case NM_MTHTR:
+ check_insn(ctx, ASE_MT);
+ gen_mttr(env, ctx, rs, rt, (ctx->opcode >> 10) & 1,
+ (ctx->opcode >> 11) & 0x1f, (ctx->opcode >> 3) & 1);
+ break;
+ case NM_YIELD:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_helper_yield(t0, cpu_env, t0);
+ gen_store_gpr(t0, rt);
+ tcg_temp_free(t0);
+ }
+ break;
#endif
default:
generate_exception_end(ctx, EXCP_RI);
@@ -17528,7 +17609,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
case NM_POOL32A:
switch (ctx->opcode & 0x07) {
case NM_POOL32A0:
- gen_pool32a0_nanomips_insn(ctx);
+ gen_pool32a0_nanomips_insn(env, ctx);
break;
case NM_POOL32A7:
switch ((ctx->opcode >> 3) & 0x07) {
--
2.7.4
