>> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
>> index 6ac8a9392da6..966a996c2eac 100644
>> --- a/include/hw/ppc/xics.h
>> +++ b/include/hw/ppc/xics.h
>> @@ -194,6 +194,7 @@ void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
>> uint32_t icp_accept(ICPState *ss);
>> uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
>> void icp_eoi(ICPState *icp, uint32_t xirr);
>> +void icp_irq(ICSState *ics, int server, int nr, uint8_t priority);
>
> Hrm... are you sure you need to expose this?
>
>> void ics_simple_write_xive(ICSState *ics, int nr, int server,
>> uint8_t priority, uint8_t saved_priority);
>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> index b9f1a3c97214..59e2a5217dcc 100644
>> --- a/hw/intc/xics.c
>> +++ b/hw/intc/xics.c
>> @@ -230,7 +230,7 @@ void icp_eoi(ICPState *icp, uint32_t xirr)
>> }
>> }
>>
>> -static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
>> +void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
>> {
>> ICPState *icp = xics_icp_get(ics->xics, server);
>>
[ ... ]
>> +
>> +static void phb3_msi_try_send(Phb3MsiState *msi, int srcno, bool ignore_p)
>> +{
>> + ICSState *ics = ICS_BASE(msi);
>> + uint64_t ive;
>> + uint64_t server, prio, pq, gen;
>> +
>> + if (!phb3_msi_read_ive(msi->phb, srcno, &ive)) {
>> + return;
>> + }
>> +
>> + server = GETFIELD(IODA2_IVT_SERVER, ive);
>> + prio = GETFIELD(IODA2_IVT_PRIORITY, ive);
>> + pq = GETFIELD(IODA2_IVT_Q, ive);
>> + if (!ignore_p) {
>> + pq |= GETFIELD(IODA2_IVT_P, ive) << 1;
>> + }
>> + gen = GETFIELD(IODA2_IVT_GEN, ive);
>> +
>> + /*
>> + * The low order 2 bits are the link pointer (Type II interrupts).
>> + * Shift back to get a valid IRQ server.
>> + */
>> + server >>= 2;
>> +
>> + switch (pq) {
>> + case 0: /* 00 */
>> + if (prio == 0xff) {
>> + /* Masked, set Q */
>> + phb3_msi_set_q(msi, srcno);
>> + } else {
>> + /* Enabled, set P and send */
>> + phb3_msi_set_p(msi, srcno, gen);
>> + icp_irq(ics, server, srcno + ics->offset, prio);
>
> Can't you just pulse the right qirq here, which will use the core ICS
> logic to propagate to the ICP?
The interrupt vector entries are maintained in the guest memory. We don't
have an entry in the device model (hcall, mmio on a register) to update
an IRQ state. So we need to find the target when the IRQ is triggered.
The interrupt source unit logic of the phb3 device is closer to the Type 3
architecture (XIVE) in fact.
C.
