On 11 February 2011 09:52, Santosh <stardi...@gmail.com> wrote: > Will QEMU arm target support Cortex-M4 FPU, ARMv7-M Floating-Point > Extension FPv4? > I don't see cortex-m4 in the cpu list. Is there any plan to support it?
Linaro's focus is on the ARM A profile, so we (I) don't have any current plans to add M4 support to QEMU. I'll happily review patches if anybody else wants to add the support, though; I'm pretty familiar with the M profile architecture. Adding the FP instructions themselves should mostly be a matter of setting up suitable feature flags so that we use the currently implemented code. The tricky part is likely to be in the support for lazy FPU stacking on exceptions. (You can set the core up so that when you take an exception only the integer registers are stored to the stack; a hole is left for the FP regs, and the first time you try to execute an FP instruction in the exception handler the core automatically saves the FP regs into the hole. Doing this means you need to be able to say for each FP instruction you're about to execute "if the core is in this state then do something special". There's no current support in the ARM target for that and you'd need to be careful to implement it so as not to slow things down massively.) -- PMM
