> Subject: [PATCH v2 18/33] target/mips: Add handling of branch delay slots for
> nanoMIPS
>
> From: Matthew Fortune <matthew.fort...@mips.com>
>
> ISA mode bit (LSB of address) is no longer required but is also
> masked to allow for tools transition. The flag has_isa_mode has the
> key role in the implementation.
>
> Signed-off-by: Yongbok Kim <yongbok....@mips.com>
> Signed-off-by: Aleksandar Markovic <amarko...@wavecomp.com>
> Signed-off-by: Stefan Markovic <smarko...@wavecomp.com>
> ---
> target/mips/translate.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 564d459..c9087d2 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1458,6 +1458,7 @@ typedef struct DisasContext {
> bool mrp;
> bool nan2008;
> bool abs2008;
> + bool has_isa_mode;
> } DisasContext;
>
> #define DISAS_STOP DISAS_TARGET_0
> @@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
>
> if (blink > 0) {
> int post_delay = insn_bytes + delayslot_size;
> - int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
> + int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
>
> tcg_gen_movi_tl(cpu_gpr[blink],
> ctx->base.pc_next + post_delay + lowbit);
> @@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int
> insn_bytes)
> break;
> case MIPS_HFLAG_BR:
> /* unconditional branch to register */
> - if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
> + if (ctx->has_isa_mode &&
> + (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {
> TCGv t0 = tcg_temp_new();
> TCGv_i32 t1 = tcg_temp_new_i32();
>
> @@ -11027,7 +11029,7 @@ static void gen_compute_compact_branch(DisasContext
> *ctx, uint32_t > opc,
> int bcond_compute = 0;
> TCGv t0 = tcg_temp_new();
> TCGv t1 = tcg_temp_new();
> - int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
> + int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) !=
> 0);
>
> if (ctx->hflags & MIPS_HFLAG_BMASK) {
> #ifdef MIPS_DEBUG_DISAS
> @@ -24749,6 +24751,7 @@ static void
> mips_tr_init_disas_context(DisasContextBase *dcbase, > CPUState *cs)
> ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
> ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
> ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> + ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
The architecture documentation for CP0 MMAR register says that "!= 3;" should
actually read "< 3;". Also, is "has_isa_mode" the best name? Would
"is_no_nanomips" be better? Or "is_nanomips", with reverse logic in the code?
> restore_cpu_state(env, ctx);
> #ifdef CONFIG_USER_ONLY
> ctx->mem_idx = MIPS_HFLAG_UM;
> --
> 2.7.4
>
>
