On 07/05/2018 07:25 PM, Jason J. Herne wrote:
Instead of doing this
> +void await_io_int(uint16_t sch_no)
> +{
> + /*
> + * wait_psw and ctl6 must be static to avoid stack allocation as gcc
> cannot
> + * align stack variables. The stctg, lctlg and lpswe instructions require
> + * that their operands be aligned on an 8-byte boundary.
> + */
> + static uint64_t ctl6 __attribute__((__aligned__(8)));
> + static PSW wait_psw;
> +
> + /* PSW to load when I/O interrupt happens */
> + lowcore->io_new_psw.mask = PSW_MASK_ZMODE;
> + lowcore->io_new_psw.addr = (uint64_t)&&IOIntWakeup; /* Wake-up address */
> +
> + /* Enable io interrupts subclass mask */
> + asm volatile("stctg 6,6,%0" : "=S" (ctl6) : : "memory");
> + ctl6 |= 0x00000000FF000000;
> + asm volatile("lctlg 6,6,%0" : : "S" (ctl6));
> +
> + /* Set wait psw enabled for io interrupt */
> + wait_psw.mask = (PSW_MASK_ZMODE | PSW_MASK_IOINT | PSW_MASK_WAIT);
> + asm volatile("lpswe %0" : : "Q" (wait_psw) : "cc");
> +
> + panic("await_io_int: lpswe failed!!\n");
> +
> +IOIntWakeup:
> + /* Should never happen - all other subchannels are disabled by default */
> + IPL_assert(lowcore->subchannel_nr == sch_no,
> + "Interrupt from unexpected device");
> +
> + /* Disable all subclasses of I/O interrupts for this cpu */
> + asm volatile("stctg 6,6,%0" : "=S" (ctl6) : : "memory");
> + ctl6 &= ~(0x00000000FF000000);
> + asm volatile("lctlg 6,6,%0" : : "S" (ctl6));
> +}
Can you please add something like consume_sclp_interrupt in start.S?
Jumping inside a function from an interrupt can mess up the stack
and possibly other things as gcc does not expect this. (you do a
longjmp without doing any precaution)
This might explain why you needed the static hack for the variables.
