On Wed, Feb 09, 2011 at 04:27:25PM +0000, Peter Maydell wrote:
> Add a float16 type to softfloat, rather than using bits16 directly.
> Also add the missing functions float16_is_quiet_nan(),
> float16_is_signaling_nan() and float16_maybe_silence_nan(),
> which are needed for the float16 conversion routines.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> fpu/softfloat-specialize.h | 59
> ++++++++++++++++++++++++++++++++++++++++++++
> fpu/softfloat.c | 8 +++---
> fpu/softfloat.h | 12 +++++++-
> 3 files changed, 73 insertions(+), 6 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index eb644b2..bc9a66c 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -57,6 +57,65 @@ typedef struct {
> } commonNaNT;
>
>
> /*----------------------------------------------------------------------------
> +| The pattern for a default generated half-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_ARM)
> +#define float16_default_nan 0x7E00
> +#elif SNAN_BIT_IS_ONE
> +#define float16_default_nan 0x7DFF
> +#else
> +#define float16_default_nan 0xFE00
> +#endif
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the half-precision floating-point value `a' is a quiet
> +| NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +int float16_is_quiet_nan(float16 a)
> +{
> +#if SNAN_BIT_IS_ONE
> + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
> +#else
> + return ((a & ~0x8000) >= 0x7c80);
> +#endif
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns 1 if the half-precision floating-point value `a' is a signaling
> +| NaN; otherwise returns 0.
> +*----------------------------------------------------------------------------*/
> +
> +int float16_is_signaling_nan(float16 a)
> +{
> +#if SNAN_BIT_IS_ONE
> + return ((a & ~0x8000) >= 0x7c80);
> +#else
> + return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
> +#endif
> +}
> +
> +/*----------------------------------------------------------------------------
> +| Returns a quiet NaN if the half-precision floating point value `a' is a
> +| signaling NaN; otherwise returns `a'.
> +*----------------------------------------------------------------------------*/
> +float16 float16_maybe_silence_nan(float16 a)
> +{
> + if (float16_is_signaling_nan(a)) {
> +#if SNAN_BIT_IS_ONE
> +# if defined(TARGET_MIPS) || defined(TARGET_SH4)
> + return float16_default_nan;
> +# else
> +# error Rules for silencing a signaling NaN are target-specific
> +# endif
> +#else
> + a |= (1 << 9);
> +#endif
> + }
> + return a;
> +}
> +
> +/*----------------------------------------------------------------------------
> | The pattern for a default generated single-precision NaN.
>
> *----------------------------------------------------------------------------*/
> #if defined(TARGET_SPARC)
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index 17842f4..dc4492a 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -2713,15 +2713,15 @@ float32 float64_to_float32( float64 a STATUS_PARAM )
> | than the desired result exponent whenever `zSig' is a complete, normalized
> | significand.
>
> *----------------------------------------------------------------------------*/
> -static bits16 packFloat16(flag zSign, int16 zExp, bits16 zSig)
> +static float16 packFloat16(flag zSign, int16 zExp, bits16 zSig)
> {
> return (((bits32)zSign) << 15) + (((bits32)zExp) << 10) + zSig;
> }
>
> /* Half precision floats come in two formats: standard IEEE and "ARM" format.
> The latter gains extra exponent range by omitting the NaN/Inf encodings.
> */
> -
> -float32 float16_to_float32( bits16 a, flag ieee STATUS_PARAM )
> +
> +float32 float16_to_float32(float16 a, flag ieee STATUS_PARAM)
> {
> flag aSign;
> int16 aExp;
> @@ -2753,7 +2753,7 @@ float32 float16_to_float32( bits16 a, flag ieee
> STATUS_PARAM )
> return packFloat32( aSign, aExp + 0x70, aSig << 13);
> }
>
> -bits16 float32_to_float16( float32 a, flag ieee STATUS_PARAM)
> +float16 float32_to_float16(float32 a, flag ieee STATUS_PARAM)
> {
> flag aSign;
> int16 aExp;
> diff --git a/fpu/softfloat.h b/fpu/softfloat.h
> index 4a5345c..f773d67 100644
> --- a/fpu/softfloat.h
> +++ b/fpu/softfloat.h
> @@ -118,6 +118,7 @@ enum {
> sane ABI should be able to see though these structs. However
> x86/gcc 3.x seems to struggle a bit, so leave them disabled by default.
> */
> //#define USE_SOFTFLOAT_STRUCT_TYPES
> +typedef uint16_t float16;
> #ifdef USE_SOFTFLOAT_STRUCT_TYPES
> typedef struct {
> uint32_t v;
You should also add it in the USE_SOFTFLOAT_STRUCT_TYPES case, so that
we can check the type correctness. Last time I tried, it was not
compiling in this mode, but it's probably worth having it anyway so that
16-bit floating points values are tested.
> @@ -253,8 +254,15 @@ float128 int64_to_float128( int64_t STATUS_PARAM );
>
> /*----------------------------------------------------------------------------
> | Software half-precision conversion routines.
>
> *----------------------------------------------------------------------------*/
> -bits16 float32_to_float16( float32, flag STATUS_PARAM );
> -float32 float16_to_float32( bits16, flag STATUS_PARAM );
> +float16 float32_to_float16( float32, flag STATUS_PARAM );
> +float32 float16_to_float32( float16, flag STATUS_PARAM );
> +
> +/*----------------------------------------------------------------------------
> +| Software half-precision operations.
> +*----------------------------------------------------------------------------*/
> +int float16_is_quiet_nan( float16 );
> +int float16_is_signaling_nan( float16 );
> +float16 float16_maybe_silence_nan( float16 );
>
>
> /*----------------------------------------------------------------------------
> | Software IEC/IEEE single-precision conversion routines.
Otherwise looks pretty good.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net
