On 3 July 2018 at 10:31, Stefan Hajnoczi <stefa...@gmail.com> wrote: > On Mon, Jul 02, 2018 at 01:18:35PM +0100, Peter Maydell wrote: >> It's not clear to me what this device is doing with its >> AddressSpace, though; comments that went into more detail >> about what the device is and what the "memory" property is >> for might help. > > I understand this issue now. It's the same as qtest. > > This device is only visible from cpu->as, it's not visible from > address_space_memory (system_memory). > > The NVMC needs access to the SoC's flash memory region, and that's what > mr/as achieve here. I agree that comments explaining the purpose of > mr/as would be useful.
Is the flash memory region only accessible to the CPU via the NVMC, or can the CPU get at it both directly and via the NVMC? (That is, in hardware, does the flash sit "behind" the NVMC?) thanks -- PMM
