On 06/26/2018 05:57 PM, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
>> This is a model of the PCIe host bridge found on Power8 chips,
>> including PowerBus logic interface, IOMMU support, PCIe root complex,
>> XICS MSI and LSI interrupt sources.
>>
>> 4 PHBs are provisioned under the Power8 chip model to fit hardware but
>> only one is currently initialized.
>
> What's the advantage in creating 4 PHBs instead of a single one,
The Power8 chip comes in different flavors: Venice, Murano, Naple,
each having a different number of PHBs. We don't need to initialize
them all to plug only a couple of devices (net, storage, usbs)
When time comes, we might want to test some more complex configurations
or extend the modeling with CAPI support. That's why we have a :
#define PNV_MAX_CHIP_PHB 4
PnvPHB3 phbs[PNV_MAX_CHIP_PHB];
under the chip, and a 'num_phbs' attribute to increase the number
of controllers. It still needs to be tested but that's the goal.
> like we already do for pSeries guests?
I didn't follow that discussion but this is "another" kind of PHB.
This one models the baremetal controller as found on OpenPOWER and
IBM Power machines. pSeries has a virtual PHB.
> As it is, this will confuse the heck out of libvirt's PCI address >
> allocation algorithm :)
The pci bus name should be directly related to the PHB index. But
I agree we need to be careful. That's why you are in cc: :)
Thanks,
C.
