On Tue, Jun 05, 2018 at 10:14:13AM +0200, Cédric Le Goater wrote: > On 06/05/2018 01:10 AM, David Gibson wrote: > > On Mon, Jun 04, 2018 at 07:20:39PM +0200, Cédric Le Goater wrote: > >> POWER9 introduced a new variant of the eieio instruction using bit 6 > >> as a hint to tell the CPU it is a store-forwarding barrier. > >> > >> The usage of this eieio extension was recently added in Linux 4.17 > >> which activated the "support for a store forwarding barrier at kernel > >> entry/exit". > >> > >> This loosen the QEMU eieio instruction mask to boot newer kernel but I > >> think we should be adding a new *eieio* instruction specific to POWER9 > >> instead. I just don't know how to define an instruction variant with > >> the same op code for an ISA version. Any idea ? > > > > I think you're right that this should be done slightly differently. > > I think you can do that by adding a new instruction mask bit; say > > PPC2_MEM_EIEIO2 or whatever. You leave the existing GEN_HANDLER as > > is, add another GEN_HANDLER_E with the new mask dependent on the new > > bit, then make sure POWER9 has the new bit set, but not the old one. > > Unfortunately this doesn't work :/ QEMU considers the opcode is already > defined. May be we could test bit6 in gen_eieio ?
Yeah, I guess we'll have to.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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