On 1 June 2018 at 02:36, Shannon Zhao <zhaoshengl...@huawei.com> wrote: > While we skip the GIC_INTERNAL irqs, we don't change the register offset > accordingly. This will overlap the GICR registers value and leave the > last GIC_INTERNAL irq's registers out of update. > > Fix this by skipping the registers banked by GICR. > > Also for migration compatibility if the migration source (old version > qemu) doesn't send gicd_no_migration_shift_bug = 1 to destination, then > we shift the data of PPI to get the right data for SPI. > > Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 > Cc: qemu-sta...@nongnu.org > Reviewed-by: Eric Auger <eric.au...@redhat.com> > Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> > Signed-off-by: Shannon Zhao <zhaoshengl...@huawei.com> > ---
Applied to target-arm.next, thanks. -- PMM
