On Mon, May 07, 2018 at 01:52:42PM -0300, luporl wrote: > According to PowerISA, the PIR register should be readable in privileged > mode also, not only in hypervisor privileged mode. > > PowerISA 3.0 - 4.3.3 Processor Identification Register > > "Read access to the PIR is privileged; write access is not > provided."
Yes... but a little further down it says "The PIR is a hypervisor
resource". Looking at the older 2.07 ISA, it says that
guest-supervisor mode reads to the PIR should be redirected to the
GPIR register, which this change won't accomplish.
So, I'm not sure what to make of this.
>
> Cc: David Gibson <da...@gibson.dropbear.id.au>
> Cc: Alexander Graf <ag...@suse.de>
> Cc: qemu-...@nongnu.org
> Signed-off-by: Leandro Lupori <leandro.lup...@gmail.com>
> Reviewed-by: Jose Ricardo Ziviani <jos...@linux.ibm.com>
> Reviewed-by: Greg Kurz <gr...@kaod.org>
> ---
> Changes in v2:
> - added my Signed-off-by, maintainers CC and Jose's Reviewed-by tags
>
> Changes in v3:
> - added subsystem name, version tag and summary of changes
> - added the section of PowerISA that describes PIR access privileges
>
> target/ppc/translate_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index a72be6d121..7b56e3ffb9 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -7816,7 +7816,7 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
> /* Processor identification */
> spr_register_hv(env, SPR_PIR, "PIR",
> SPR_NOACCESS, SPR_NOACCESS,
> - SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, SPR_NOACCESS,
> &spr_read_generic, NULL,
> 0x00000000);
> spr_register_hv(env, SPR_HID0, "HID0",
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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