On Sun, May 27, 2018 at 09:13:12AM -0500, Richard Henderson wrote: > There is no reason to allocate this separately. This was probably > copied from target/mips which makes the same mistake. > > While doing so, move tlb into the clear-on-reset range. While not > all of the TLB bits are guaranteed zero on reset, all of the valid > bits are cleared, and the rest of the bits are unspecified. > Therefore clearing the whole of the TLB is correct. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Stafford Horne <sho...@gmail.com> > target/openrisc/cpu.h | 6 ++++-- > target/openrisc/interrupt.c | 4 ++-- > target/openrisc/interrupt_helper.c | 8 +++---- > target/openrisc/machine.c | 15 ++++++------- > target/openrisc/mmu.c | 34 ++++++++++++++---------------- > target/openrisc/sys_helper.c | 28 ++++++++++++------------ > 6 files changed, 46 insertions(+), 49 deletions(-) > > diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h > index 35cab65f11..edc06be40e 100644 > --- a/target/openrisc/cpu.h > +++ b/target/openrisc/cpu.h > @@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState { > > uint32_t dflag; /* In delay slot (boolean) */ > > +#ifndef CONFIG_USER_ONLY > + CPUOpenRISCTLBContext tlb; > +#endif > + > /* Fields up to this point are cleared by a CPU reset */ > struct {} end_reset_fields; > > @@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState { > uint32_t cpucfgr; /* CPU configure register */ > > #ifndef CONFIG_USER_ONLY > - CPUOpenRISCTLBContext * tlb; > - > QEMUTimer *timer; > uint32_t ttmr; /* Timer tick mode register */ > int is_counting; [...] > > diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c > index 0a793eb14d..c10d28b055 100644 > --- a/target/openrisc/machine.c > +++ b/target/openrisc/machine.c > @@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id) > > /* Restore MMU handlers */ > if (env->sr & SR_DME) { > - env->tlb->cpu_openrisc_map_address_data = > + env->tlb.cpu_openrisc_map_address_data = > &cpu_openrisc_get_phys_data; > } else { > - env->tlb->cpu_openrisc_map_address_data = > + env->tlb.cpu_openrisc_map_address_data = > &cpu_openrisc_get_phys_nommu; > } > > if (env->sr & SR_IME) { > - env->tlb->cpu_openrisc_map_address_code = > + env->tlb.cpu_openrisc_map_address_code = > &cpu_openrisc_get_phys_code; > } else { > - env->tlb->cpu_openrisc_map_address_code = > + env->tlb.cpu_openrisc_map_address_code = > &cpu_openrisc_get_phys_nommu; > } > > @@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb = { > } > }; > > -#define VMSTATE_CPU_TLB(_f, _s) \ > - VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) > - > - > static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField > *field) > { > CPUOpenRISCState *env = opaque; > @@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env = { > VMSTATE_UINT32(fpcsr, CPUOpenRISCState), > VMSTATE_UINT64(mac, CPUOpenRISCState), > > - VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), > + VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1, > + vmstate_cpu_tlb, CPUOpenRISCTLBContext), As discussed no need for version update here since no actual change to serialized bits. > > VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), > VMSTATE_UINT32(ttmr, CPUOpenRISCState),