From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Add a R_TBLX_MISS MASK and SHIFT macros.
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/microblaze/mmu.c | 5 +++--
target/microblaze/mmu.h | 4 ++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 0019ebd18f..f4a4c339c9 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -292,8 +292,9 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
v & TLB_EPN_MASK, 0, cpu_mmu_index(env,
false));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
- } else
- env->mmu.regs[MMU_R_TLBX] |= 0x80000000;
+ } else {
+ env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
+ }
break;
}
default:
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 3b7a9983d5..113539c6e9 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -54,6 +54,10 @@
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
+/* TLBX */
+#define R_TBLX_MISS_SHIFT 31
+#define R_TBLX_MISS_MASK (1U << R_TBLX_MISS_SHIFT)
+
#define TLB_ENTRIES 64
struct microblaze_mmu
--
2.14.1
