On 05/03/2018 02:19 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Extend special registers to 64-bits. This is in preparation for
> MFSE/MTSE, moves to and from extended special registers.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
> @@ -1124,13 +1125,13 @@ static inline void eval_cc(DisasContext *dc, unsigned
> int cc,
> }
> }
>
> -static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32
> pc_false)
> +static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i64
> pc_false)
> {
> TCGLabel *l1 = gen_new_label();
> /* Conditional jmp. */
> - tcg_gen_mov_i32(cpu_SR[SR_PC], pc_false);
> + tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false);
> tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1);
> - tcg_gen_mov_i32(cpu_SR[SR_PC], pc_true);
> + tcg_gen_extu_i32_i64(cpu_SR[SR_PC], pc_true);
> gen_set_label(l1);
> }
For future cleanup, this should use tcg_gen_movcond_i32.
r~
