Richard Henderson <richard.hender...@linaro.org> writes:
> Use write_fp_dreg and clear_vec_high to zero the bits
> that need zeroing for these cases.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/translate-a64.c | 17 +++++------------
> 1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index b27892d971..f2241d8174 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -5356,31 +5356,24 @@ static void handle_fmov(DisasContext *s, int rd, int
> rn, int type, bool itof)
>
> if (itof) {
> TCGv_i64 tcg_rn = cpu_reg(s, rn);
> + TCGv_i64 tmp;
>
> switch (type) {
> case 0:
> - {
> /* 32 bit */
> - TCGv_i64 tmp = tcg_temp_new_i64();
> + tmp = tcg_temp_new_i64();
> tcg_gen_ext32u_i64(tmp, tcg_rn);
> - tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
> - tcg_gen_movi_i64(tmp, 0);
> - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
> + write_fp_dreg(s, rd, tmp);
> tcg_temp_free_i64(tmp);
> break;
> - }
> case 1:
> - {
> /* 64 bit */
> - TCGv_i64 tmp = tcg_const_i64(0);
> - tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
> - tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
> - tcg_temp_free_i64(tmp);
> + write_fp_dreg(s, rd, tcg_rn);
> break;
> - }
> case 2:
> /* 64 bit to top half. */
> tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
> + clear_vec_high(s, true, rd);
I was going to suggest maybe a write_fp_dreg_hi() helper here but there
are only a couple of cases so:
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> break;
> }
> } else {
--
Alex Bennée
