On 3/20/2018 3:12 PM, Igor Mammedov wrote:
On Tue, 20 Mar 2018 13:29:24 +0800 "Qin, Chao" > <chao....@linux.intel.com> wrote: > >> On 3/20/2018 12:05 AM, Igor
Mammedov wrote: >>> On Mon, 19 Mar 2018 17:04:49 +0800
chao....@linux.intel.com >>> wrote: > >> From: Qin Chao
<chao....@intel.com> > / something horribly wrong with mail client used
for reply / >
Very sorry for the wrong reply style.
@@ >> -933,6 +944,9 @@ static int hax_set_msrs(CPUArchState *env) >> >>
hax_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); >> >>
hax_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, >> >>
env->kernelgsbase); #endif + hax_msr_entry_set(&msrs[n++], >> >>
MSR_IA32_APICBASE, \ + >> >>
cpu_get_apic_base(x86_env_get_cpu(env)->apic_state)); + md.nr_msr = >>
>> n; md.done = 0; > Does it work for you if you drop everything >>
except of this chunk? Yes, it works just with this chunk. > Could you
send v2 dropping unnecessary chunks pls? (provided that > Paolo would
drop queued v1).
I think you may missed the clarification for the codes that syncing
IA32_APIC_BASE MSR from HAXM to QEMU due to rhe wrong reply style.
Sorry again for the inconvenience. Please refer to the following.
Yes, the BSP is hard-coded in QEMU. But other bits, not just BSP flag, are
alse needed to sync from HAXM, such as x2APIC mode flag (bit 10) and
APIC enable/disable flag (bit 11). As in the Google Zircon
(https://github.com/fuchsia-mirror/zircon/blob/master/kernel/arch/x86/lapic.cpp#L157),
it will change IA32_APIC_BASE[10] and the the bit to 1 if x2APIC enabled.
Although x2APIC mode is not supported yet for TCG mode, it's worthy to
keep the codes that syncing IA32_APIC_BASE from HAXM to QEMU and
if x2APIC mode is supported fro TCG in future, there is no any effort needed
to make HAXM to work with this mode. Alos, in KVM it synced the
IA32_APIC_BASE
MSR to QEMU at every VM-Exit.
