Patch which should fix this:
https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg04537.html
** Changed in: qemu
Status: New => In Progress
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https://bugs.launchpad.net/bugs/1748434
Title:
Possibly wrong GICv3 behavior when secure enabled
Status in QEMU:
In Progress
Bug description:
I an tried arm-aarch64 interrupt routing to EL3, by SCR_EL3.FIQ=1. First I am
started QEMU with secure=on and GICv3 support.
I programmed secure and non-secure timers and set-up appropriate
interrupts.Secure timer to be GRP1_Secure and non-secure timer to be
GRP1_NonSecure. ICC_PMR = 0xff. Then I switched CPU to EL1.
With that setup no interrupt was delivered to PE. GIC interface showed that
non secure IRQ is pending. ICC_PMR read at EL1 returns 0 (shall return value
((PMR_(el3) << 1) & 0xff) according to GIC specification.
Than I tried to increase interrupt priority mask - so I set ICC_PMR = 0x7f
(at EL3). Then I read at EL1 ICC_PMR=0xfe - (is shall be 0). With this setup
IRQ of secure timer was taken at EL3, non secure timer didn't rise IRQ (as it
is masked by PMR).
I dig to qemu code and see wrong condition in file arm_gicv3_cpuif.c in
function icc_pmr_read(). This behavior is opposite of ARM specification.
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