Le 14/03/2018 à 16:31, James Cowgill a écrit : > Add support for the two currently defined HWCAP bits on MIPS - R6 and > MSA. > > Buglink: https://bugs.launchpad.net/qemu/+bug/1754372 > Signed-off-by: James Cowgill <james.cowg...@mips.com> > --- > This was resent because I think I messed up my email config. Apologies if you > receive this twice. > > linux-user/elfload.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 5fc130cc20..747b0ed10b 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -950,6 +950,30 @@ static void elf_core_copy_regs(target_elf_gregset_t > *regs, const CPUMIPSState *e > #define USE_ELF_CORE_DUMP > #define ELF_EXEC_PAGESIZE 4096 > > +/* See arch/mips/include/uapi/hwcap.h. */
in fact arch/mips/include/uapi/asm/hwcap.h > +enum { > + HWCAP_MIPS_R6 = (1 << 0), > + HWCAP_MIPS_MSA = (1 << 1), > +}; We have this for ARM only in elfload.c since: afce2927aa Arm AT_HWCAP AUXV entry (Paul Brook) [2005] but they have been added in include/elf.h since: 41d9ea80ac tcg-arm: Use qemu_getauxval [Richard Henderson, 2013] and I think we should remove them (they are prefixed by ARM_) So the MIPS ones should be in include/elf.h (with the #define form). Richard, any comment? Thanks, Laurent