On Tue, Jan 11, 2011 at 10:12:10PM +0000, Peter Maydell wrote: > This patchset corrects a number of places in the ARM translation code > which were generating code which was dependent on values in the CPUState > structure which might change at runtime. This is a bad idea for two > reasons. Firstly, we might try to reuse the generated code later when > the assumptions baked into the generated code were no longer valid. > Secondly, we might try to retranslate the same TB (eg when an exception > results in our calling cpu_restore_state()) but get different generated > code, which could result in qemu crashing. > > Bug https://bugs.launchpad.net/bugs/604872 is a particular example > of the latter case involving the IT bits; this patchset fixes that bug. > > I believe that this patchset deals with all the problems. Remaining > CPUState fields referred to in translate.c are either constant after > system init or trigger flushing of affected TBs when they are changed. > > Differences from v1: I've added some macros for the TB flags bitfields, > as suggested by Aurelien. > > Peter Maydell (8): > target-arm: Don't generate code specific to current CPU mode for SRS > target-arm: Add symbolic constants for bitfields in TB flags > target-arm: Translate with VFP-enabled from TB flags, not CPUState > target-arm: Translate with VFP len/stride from TB flags, not CPUState > target-arm: Translate with Thumb state from TB flags, not CPUState > target-arm: Translate with condexec bits from TB flags, not CPUState > target-arm: Set privileged bit in TB flags correctly for M profile > target-arm: Translate with user-state from TB flags, not CPUState > > target-arm/cpu.h | 51 ++++++++++++++++++++++++--- > target-arm/helper.c | 12 +++++- > target-arm/translate.c | 88 ++++++++++++++++++----------------------------- > 3 files changed, 89 insertions(+), 62 deletions(-) > > >
Thanks, all applied. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurel...@aurel32.net http://www.aurel32.net
