On 27 February 2018 at 20:18, Richard Henderson <richard.hender...@linaro.org> wrote: > On 02/20/2018 10:03 AM, Peter Maydell wrote: >> + env->v7m.vecbase[M_REG_S] = cpu->init_svtor; > > Perhaps & ~0x3f here; that part of the field is RES0. > > That said, if the only setter of this property is within qemu code, and not > from the command line, then I suppose it doesn't matter in practice.
Bits 6..0 are RES0, not just 5..0. I've added "& 0xffffff80" (to match how we do the masking in the VTOR write code path in armv7m_nvic.c). thanks -- PMM
