Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180223153636.29809-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH v3 00/31] Add ARMv8.2 half-precision functions
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
973d6ea847 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
865c5efee7 arm/translate-a64: implement simd_scalar_three_reg_same_fp16
fd1fec9d84 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
34a9ee1b72 arm/translate-a64: add FP16 FMOV to simd_mod_imm
e61c7193a5 arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
dbbbc15721 arm/helper.c: re-factor rsqrte and add rsqrte_f16
1f776415c0 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
01a7993654 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
3e2b3ca80f arm/translate-a64: add FP16 FRECPE
33514ae31f arm/helper.c: re-factor recpe and add recepe_f16
a1dfb85e0f arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
92e3338b5a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
5b86cb374f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
17e2eee31c arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
893c84283a arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
c29baaf9c1 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
714d9395cc arm/translate-a64: add FP16 x2 ops for simd_indexed
b026878d1c arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
ea0357c725 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
dfbe2602d6 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
c17489ca3b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
e4fa306574 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to
simd_three_reg_same_fp16
688c5a1edc arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to
simd_three_reg_same_fp16
3d44f35de5 arm/translate-a64: initial decode for simd_three_reg_same_fp16
db5773e357 arm/translate-a64: handle_3same_64 comment fix
2e96f5c4ee arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
278b916615 target/arm/helper: pass explicit fpst to set_rmode
4ef0855eb3 target/arm/cpu.h: add additional float_status flags
9360101ac7 target/arm/cpu.h: update comment for half-precision values
7a30500e92 target/arm/cpu64: introduce ARM_V8_FP16 feature bit
47fba618d4 include/exec/helper-head.h: support f16 in helper calls
=== OUTPUT BEGIN ===
Checking PATCH 1/31: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 2/31: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 3/31: target/arm/cpu.h: update comment for half-precision
values...
Checking PATCH 4/31: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 5/31: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 6/31: arm/translate-a64: implement half-precision
F(MIN|MAX)(V|NMV)...
Checking PATCH 7/31: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 8/31: arm/translate-a64: initial decode for
simd_three_reg_same_fp16...
Checking PATCH 9/31: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to
simd_three_reg_same_fp16...
Checking PATCH 10/31: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to
simd_three_reg_same_fp16...
Checking PATCH 11/31: arm/translate-a64: add FP16 FMULA/X/S to
simd_three_reg_same_fp16...
Checking PATCH 12/31: arm/translate-a64: add FP16 FR[ECP/SQRT]S to
simd_three_reg_same_fp16...
Checking PATCH 13/31: arm/translate-a64: add FP16 pairwise ops
simd_three_reg_same_fp16...
Checking PATCH 14/31: arm/translate-a64: add FP16 FMULX/MLS/FMLA to
simd_indexed...
Checking PATCH 15/31: arm/translate-a64: add FP16 x2 ops for simd_indexed...
Checking PATCH 16/31: arm/translate-a64: initial decode for
simd_two_reg_misc_fp16...
Checking PATCH 17/31: arm/translate-a64: add FP16 FPRINTx to
simd_two_reg_misc_fp16...
Checking PATCH 18/31: arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16...
Checking PATCH 19/31: arm/translate-a64: add FP16 FCMxx (zero) to
simd_two_reg_misc_fp16...
Checking PATCH 20/31: arm/translate-a64: add FP16 SCVTF/UCVFT to
simd_two_reg_misc_fp16...
ERROR: space prohibited before that close parenthesis ')'
#26: FILE: target/arm/helper.c:11305:
+FLOAT_CONVS(si, h, 16, )
total: 1 errors, 0 warnings, 208 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 21/31: arm/translate-a64: add FP16 FNEG/FABS to
simd_two_reg_misc_fp16...
Checking PATCH 22/31: arm/helper.c: re-factor recpe and add recepe_f16...
Checking PATCH 23/31: arm/translate-a64: add FP16 FRECPE...
Checking PATCH 24/31: arm/translate-a64: add FP16 FRCPX to
simd_two_reg_misc_fp16...
Checking PATCH 25/31: arm/translate-a64: add FP16 FSQRT to
simd_two_reg_misc_fp16...
Checking PATCH 26/31: arm/helper.c: re-factor rsqrte and add rsqrte_f16...
Checking PATCH 27/31: arm/translate-a64: add FP16 FRSQRTE to
simd_two_reg_misc_fp16...
Checking PATCH 28/31: arm/translate-a64: add FP16 FMOV to simd_mod_imm...
Checking PATCH 29/31: arm/translate-a64: add all FP16 ops in
simd_scalar_pairwise...
Checking PATCH 30/31: arm/translate-a64: implement
simd_scalar_three_reg_same_fp16...
Checking PATCH 31/31: arm/translate-a64: add all single op FP16 to
handle_fp_1src_half...
=== OUTPUT END ===
Test command exited with code: 1
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