On 02/19/2018 07:18 AM, David Brenken wrote:
> From: David Brenken <david.bren...@efs-auto.de>
>
> + case OPC1_16_SBR_JEQ2:
> + gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
> + offset + 16);
> + break;
This is a 1.6+ instruction and you need to add a check, like with
OPC2_32_RR_MOVS_64.
> case OPC1_16_SBR_JNE:
> gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
> offset);
> break;
> + case OPC1_16_SBR_JNE2:
> + gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
> + offset + 16);
> + break;
Likewise.
> case OPC1_16_SBR_JNZ:
> gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
> break;
> @@ -4089,6 +4097,10 @@ static void decode_16Bit_opc(CPUTriCoreState *env,
> DisasContext *ctx)
> gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4,
> MO_LESL);
> break;
> /* SB-format */
> + case OPC1_16_SB_JNE:
> + address = MASK_OP_SBC_DISP4(ctx->opcode);
> + gen_compute_branch(ctx, op1, 0, 0, 0, address);
> + break;
Why duplicate the code here? First, OPC1_16_SB_JNE is the same opcode as
OPC1_16_SBR_JNE2. Second, you can just add your case below
OPC1_16_SBR_JNE in decode_16Bit_opc().
> @@ -321,11 +322,13 @@ enum {
> OPC1_16_SBC_JNE = 0x5e,
> OPC1_16_SBC_JNE2 = 0xde,
> OPC1_16_SBR_JNE = 0x7e,
> + OPC1_16_SBR_JNE2 = 0xfe,
> OPC1_16_SB_JNZ = 0xee,
> OPC1_16_SBR_JNZ = 0xf6,
> OPC1_16_SBR_JNZ_A = 0x7c,
> OPC1_16_SBRN_JNZ_T = 0xae,
> OPC1_16_SB_JZ = 0x6e,
> + OPC1_16_SB_JNE = 0xfe,
This is the same opcode as OPC1_16_SBR_JNE2. Don't duplicate it.
