> Changes since v1:
> * Pass pycodestyle-{2,3}.
> * Support 16-bit and 32-bit insns (I have a def file for thumb1).
For the record, here's the thumb1 definition.
./scripts/decodetree.py -w16 thumb1.def
r~
%reg_0_7 7:1 0:3
@rd_rs ...... .... rs:3 rd:3
@rt_rn_rm .... ... rm:3 rn:3 rt:3
@rd_rn_rm .... ... rm:3 rn:3 rd:3
@rd_rn_i3 .... ... imm:3 rn:3 rd:3
@rt_rn_i5 ..... imm:5 rn:3 rt:3
@rd_i8 ..... rd:3 imm:8
@rn_reglist ..... rn:3 reglist:8
#### Data Processing (two low registers)
AND 010000 0000 ... ... @rd_rs
EOR 010000 0001 ... ... @rd_rs
MOV_lsl 010000 0010 ... ... @rd_rs
MOV_lsr 010000 0011 ... ... @rd_rs
MOV_asr 010000 0100 ... ... @rd_rs
ADC 010000 0101 ... ... @rd_rs
SBC 010000 0110 ... ... @rd_rs
MOV_ror 010000 0111 ... ... @rd_rs
TST 010000 1000 ... ... @rd_rs
RSB 010000 1001 ... ... @rd_rs
CMP_rr 010000 1010 ... ... @rd_rs
CMN 010000 1011 ... ... @rd_rs
ORR 010000 1100 ... ... @rd_rs
MUL 010000 1101 ... ... @rd_rs
BIC 010000 1110 ... ... @rd_rs
MVN 010000 1111 ... ... @rd_rs
#### Load/store (register offset)
STR_rr 0101 000 ... ... ... @rt_rn_rm
STRH_rr 0101 001 ... ... ... @rt_rn_rm
STRB_rr 0101 010 ... ... ... @rt_rn_rm
LDRSB_rr 0101 011 ... ... ... @rt_rn_rm
LDR_rr 0101 100 ... ... ... @rt_rn_rm
LDRH_rr 0101 101 ... ... ... @rt_rn_rm
LDRB_rr 0101 110 ... ... ... @rt_rn_rm
LDRSH_rr 0101 111 ... ... ... @rt_rn_rm
#### Load/store word/byte (immediate offset)
STR_ri 01100 ..... ... ... @rt_rn_i5
LDR_ri 01101 ..... ... ... @rt_rn_i5
STRB_ri 01110 ..... ... ... @rt_rn_i5
LDRB_ri 01111 ..... ... ... @rt_rn_i5
#### Load/store halfword (immediate offset)
STRH_ri 10000 ..... ... ... @rt_rn_i5
LDRH_ri 10001 ..... ... ... @rt_rn_i5
#### Add PC/SP (immediate)
ADR 10100 ... ........ @rd_i8
ADD_sp 10101 ... ........ @rd_i8
#### Load/store multiple
STM 11000 ... ........ @rn_reglist
LDM 11001 ... ........ @rn_reglist
#### Add/subtract (three low registers)
ADD_rrr 0001100 ... ... ... @rd_rn_rm
SUB_rrr 0001101 ... ... ... @rd_rn_rm
#### Add/subtract (two low registers and immediate)
ADD_rri 0001 110 ... ... ... @rd_rn_i3
SUB_rri 0001 111 ... ... ... @rd_rn_i3
#### Add, subtract, compare, move (one low register and immediate)
MOV_ri 00100 ... ........ @rd_i8
CMP_ri 00101 ... ........ @rd_i8
ADD_ri 00110 ... ........ @rd_i8
SUB_ri 00111 ... ........ @rd_i8
#### Branch and exchange
BX 0100 0111 0 rm:4 000
BLX 0100 0111 1 rm:4 000
#### Add, subtract, compare, move (two high registers)
ADD_rrr 0100 0100 . rm:4 ... rd=%reg_0_7 rn=%reg_0_7
CMP_rr 0100 0101 . rs:4 ... rd=%reg_0_7
MOV_rr 0100 0110 . rs:4 ... rd=%reg_0_7
#### Adjust SP (immediate)
ADD_rri 1011 0000 0 imm:7 rd=13 rn=13
SUB_rri 1011 0000 1 imm:7 rd=13 rn=13
#### Extend
SXTH 1011 0010 00 ... ... @rd_rs
SXTB 1011 0010 01 ... ... @rd_rs
UXTH 1011 0010 10 ... ... @rd_rs
UXTB 1011 0010 11 ... ... @rd_rs
#### Change processor state
SETEND 1011 0110 010 flags:5
CPS 1011 0110 011 flags:5
#### Reverse bytes
REV 1011 1010 00 ... ... @rd_rs
REV16 1011 1010 01 ... ... @rd_rs
REVSH 1011 1010 11 ... ... @rd_rs
#### Hints
NOP 1011 1111 0000 0000
YIELD 1011 1111 0001 0000
WFE 1011 1111 0010 0000
WFI 1011 1111 0011 0000
SEV 1011 1111 0100 0000
SEVL 1011 1111 0101 0000
NOP 1011 1111 011- 0000 # Reserved hint
NOP 1011 1111 1--- 0000 # Reserved hint
#### Push and Pop
PUSH 1011 010 reglist:9
POP 1011 110 reglist:9
#### Conditional branches
Bcond 1101 0 cond:3 imm:8
Bcond 1101 1000 imm:8 cond=8
Bcond 1101 1001 imm:8 cond=9
Bcond 1101 1010 imm:8 cond=10
Bcond 1101 1011 imm:8 cond=11
Bcond 1101 1100 imm:8 cond=12
Bcond 1101 1101 imm:8 cond=13
#### Exception generation
UDF 1101 1110 imm:8
SVC 1101 1111 imm:8
