> From: Laurent Vivier [mailto:laur...@vivier.eu]
> Le 06/02/2018 à 14:30, Pavel Dovgalyuk a écrit :
> >> From: Laurent Vivier [mailto:laur...@vivier.eu]
> > Thanks!
> >
> > By the way, we also handled reset interrupt, but it is not compatible with 
> > other m68k
> platforms:
> >
> > @@ -66,8 +66,9 @@ static void m68k_cpu_reset(CPUState *s)
> >      cpu_m68k_set_fpcr(env, 0);
> >      env->fpsr = 0;
> >
> > -    /* TODO: We should set PC from the interrupt vector.  */
> > -    env->pc = 0;
> > +    env->vbr = 0;
> > +    /* PC and SP (for m68k) will be initialized by the reset handler */
> > +    s->exception_index = EXCP_RESET;
> >  }
> >
> > @@ -378,6 +380,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int 
> > is_hw)
> >          cpu_m68k_set_sr(env, sr &= ~SR_M);
> >          sp = env->aregs[7] & ~1;
> >          do_stack_frame(env, &sp, 1, oldsr, 0, retaddr);
> > +    } else if (cs->exception_index == EXCP_RESET) {
> > +        sp = cpu_ldl_kernel(env, env->vbr + vector - 4);
> >      } else {
> >          do_stack_frame(env, &sp, 0, oldsr, 0, retaddr);
> >      }
> 
> It looks better of what I have already coded :)
> 
> Do you work using code in
> https://github.com/vivier/qemu-m68k , branch q800-dev ?

No, it was a project for our students couple of years ago.
We used Qemu 2.3 with not-yet-included patches for 68000.
I believe that someday we'll port our peripherals onto the new version.

There were some fixes for processing the interrupts. As I can see, all of them 
are
not needed for the mainline Qemu.

We didn't find a solution for 24-bit address bus of 68000. Macintosh stores 
32-bit values 
in address registers and uses them to access the memory. We just duplicated the 
memory layout,
but I believe that there is a better solution.

> I'm already emulating a Quadra 800, it can help for Macintosh-128k

Here is the repository with Mac-128: https://github.com/Dovgalyuk/qemu
We didn't finally fix all the bugs, but it can boot the OS, using some hacks.
One of the hack is related to IWM. We couldn't emulate all timings for that.
CPU controls disk rotation speed through controlling the strobe signal.
It was hard to synchronize this, because icount wasn't fully working and we used
semihosting - we intercepted the file operation system calls and didn't execute
ROM code, emulating them in Qemu instead.

Pavel Dovgalyuk


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