Hi Peter, On 2018/1/26 18:01, Peter Maydell wrote: > On 26 January 2018 at 17:33, Wei Xu <xuw...@hisilicon.com> wrote: >> On 2018/1/26 17:15, Peter Maydell wrote: >>> The pl011 code should call qemu_set_irq(..., 1) when the >>> guest enables interrupts on the device by writing to the int_enabled >>> (UARTIMSC) register. That will be a 0-to-1 level change and the KVM >>> VGIC should report the interrupt to the guest. >>> >> >> Yes. >> And in the pl011_update, the irq level is set by s->int_level & >> s->int_enabled. >> When writing to the int_enabled, not sure why the int_level is set to >> 0x20(PL011_INT_TX) but int_enabled is 0x50. >> >> It still call qemu_set_irq(..., 0). >> >> I added "s->int_level |= PL011_INT_RX" before calling pl011_update >> when writing to the int_enabled and tested it also works. > > No, that's not right either. int_level should already have the > RX bit set, because pl011_put_fifo() sets that bit when it gets a > character from QEMU and puts it into the FIFO. > > Does something else clear the int_level between the character > going into the FIFO from QEMU and the guest enabling > interrupts?
Yes. When the guest enabling the interrupts, the pl011 driver in the kernel will clear the RX interrupts[1]. And pasted the code below to make it easy to read. static void pl011_enable_interrupts(struct uart_amba_port *uap) { spin_lock_irq(&uap->port.lock); /* Clear out any spuriously appearing RX interrupts */ pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); uap->im = UART011_RTIM; if (!pl011_dma_rx_running(uap)) uap->im |= UART011_RXIM; pl011_write(uap->im, uap, REG_IMSC); spin_unlock_irq(&uap->port.lock); } I tried kept the RXIS in the kernel side to test and found the issue is still there. A little confused now :( [1]: https://elixir.free-electrons.com/linux/latest/source/drivers/tty/serial/amba-pl011.c#L1732 Best Regards, Wei > > thanks > -- PMM > > . >