On 01/25/2018 08:44 AM, Peter Maydell wrote:
>> +/* Return the offset info CPUARMState of the "whole" vector register Qn. */
>> +static inline int vec_full_reg_offset(DisasContext *s, int regno)
>> +{
>> + assert_fp_access_checked(s);
>> + return offsetof(CPUARMState, vfp.regs[regno * 2]);
>> +}
>
> This function is already in the preparatory SVE code in target-arm.next,
> so it should go away on rebase...
Ok.
>
>> +
>> +/* Return the byte size of the "whole" vector register, VL / 8. */
>> +static inline int vec_full_reg_size(DisasContext *s)
>> +{
>> + /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
>> + In the meantime this is just the AdvSIMD length of 128. */
>> + return 128 / 8;
>> +}
>
> ...and this is fixed in your other patchset with the leftovers from
> that preparatory set, right? What's the plan for what sequence we
> put these into master?
I had previously assumed that this patch set would go in before all of the
other SVE prep work, though it doesn't seem to be working out that way...
I'd like this one to go in next, fwiw.
> Have you done risu-testing on this patchset?
Yes, I've run the full set of aarch64 risu tests.
r~
