Richard Henderson <richard.hender...@linaro.org> writes:
> On 01/22/2018 04:04 AM, Alex Bennée wrote:
>>
>> Richard Henderson <richard.hender...@linaro.org> writes:
>>
>>> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
>>> ---
>>> target/arm/cpu.h | 12 ++++++++++++
>>> 1 file changed, 12 insertions(+)
>>>
>>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
>>> index 57d805b5d8..132da359b5 100644
>>> --- a/target/arm/cpu.h
>>> +++ b/target/arm/cpu.h
>>> @@ -186,6 +186,15 @@ typedef struct ARMVectorReg {
>>> uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
>>> } ARMVectorReg;
>>>
>>> +/* In AArch32 mode, predicate registers do not exist at all. */
>>> +typedef struct ARMPredicateReg {
>>> +#ifdef TARGET_AARCH64
>>> + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
>>> +#else
>>> + uint64_t p[0];
>>> +#endif
>>> +} ARMPredicateReg;
>>> +
>>>
>>> typedef struct CPUARMState {
>>> /* Regs for current mode. */
>>> @@ -513,6 +522,9 @@ typedef struct CPUARMState {
>>> struct {
>>> ARMVectorReg zregs[32];
>>>
>>> + /* Store FFR as pregs[16] to make it easier to treat as any other.
>>> */
>>> + ARMPredicateReg pregs[17];
>>> +
>>
>> What happens if code tries to accidentally access this on the 32 bit build?
>
> *shrug* About what you'd expect. What do you suggest? Ifdeffery?
I think so. I'd prefer a straight compile failure to some subtle
run-time corruption. That is of course assuming the #ifdef magic doesn't
make the aarch32 support for aarch64-softmmu harder. I wouldn't say it
is a hill I want to die on ;-)
--
Alex Bennée
