On 01/18/2018 11:38 AM, Laurent Vivier wrote: > Only add MC68040 MMU page table processing and related > registers (Special Status Word, Translation Control Register, > User Root Pointer and Supervisor Root Pointer). > > Transparent Translation Registers, DFC/SFC and pflush/ptest > will be added later. > > Signed-off-by: Laurent Vivier <laur...@vivier.eu> > --- > v4: align logical/physical on TARGET_PAGE_SIZE for tlb_set_page() > v3: s/smaller/smallest/ > v2: move mmu_fault to CPUM68KState > set TARGET_PAGE_BITS to 12 to avoid tlb_add_large_page() path > use -page_size to mask address instead of TARGET_PAGE_MASK > add ACCESS_DEBUG to not update page table USED/MODIFIED bits > on gdb access > rename ACCESS_INT to ACCESS_DATA > > v2: move mmu_fault to CPUM68KState > set TARGET_PAGE_BITS to 12 to avoid tlb_add_large_page() path > use -page_size to mask address instead of TARGET_PAGE_MASK > add ACCESS_DEBUG to not update page table USED/MODIFIED bits > on gdb access > rename ACCESS_INT to ACCESS_DATA
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
