On 18 December 2017 at 17:45, Richard Henderson <richard.hender...@linaro.org> wrote: > To be used to decode ARM SVE, but could be used for any 32-bit RISC. > It would need additional work to extend to insn sizes other than 32-bit.
I guess we could make that extension without requiring all existing pattern files to be updated, right? > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > scripts/decodetree.py | 984 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 984 insertions(+) > create mode 100755 scripts/decodetree.py This is rather large for a single patch... > +# Pattern examples: > +# > +# addl_r 010000 ..... ..... .... 0000000 ..... @opr > +# addl_i 010000 ..... ..... .... 0000000 ..... @opi > +# I think we should insist that a pattern defines all the bits (either as constant values or as fields that get passed to the decode function). That will help prevent accidental under-decoding. thanks -- PMM
