On 11/28/2017 11:31 PM, Alistair Francis wrote:
Update the reset value to match the latest ZynqMP register spec.

Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
---

  hw/ssi/xilinx_spips.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ad1b2ba79f..899db814ee 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -355,6 +355,7 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d)
      s->regs[R_GQSPI_RX_THRESH] = 1;
      s->regs[R_GQSPI_GFIFO_THRESH] = 1;
      s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
+    s->regs[R_MOD_ID] = 0x01090101;

Reviewed-by: KONRAD Frederic <frederic.kon...@adacore.com>

      s->man_start_com_g = false;
      s->gqspi_irqline = 0;
      xlnx_zynqmp_qspips_update_ixr(s);


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