On Fri, Nov 24, 2017 at 08:05:50AM +0100, Cédric Le Goater wrote: > When a CPU is stopped with the 'stop-self' RTAS call, its state > 'halted' is switched to 1 and, in this case, the MSR is not taken into > account anymore in the cpu_has_work() routine. Only the pending > hardware interrupts are checked with their LPCR:PECE* enablement bit. > > The CPU is now also protected from the decrementer interrupt by the > LPCR:PECE* bits which are disabled in the 'stop-self' RTAS > call. Reseting the MSR is pointless. > > Signed-off-by: Cédric Le Goater <c...@kaod.org> > Reviewed-by: David Gibson <da...@gibson.dropbear.id.au>
Applied to ppc-for-2.12.
> ---
> hw/ppc/spapr_rtas.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
> index 858adb1bf3a9..4bb939d3d111 100644
> --- a/hw/ppc/spapr_rtas.c
> +++ b/hw/ppc/spapr_rtas.c
> @@ -206,16 +206,6 @@ static void rtas_stop_self(PowerPCCPU *cpu,
> sPAPRMachineState *spapr,
>
> cs->halted = 1;
> qemu_cpu_kick(cs);
> - /*
> - * While stopping a CPU, the guest calls H_CPPR which
> - * effectively disables interrupts on XICS level.
> - * However decrementer interrupts in TCG can still
> - * wake the CPU up so here we disable interrupts in MSR
> - * as well.
> - * As rtas_start_cpu() resets the whole MSR anyway, there is
> - * no need to bother with specific bits, we just clear it.
> - */
> - env->msr = 0;
>
> /* Disable Power-saving mode Exit Cause exceptions for the CPU.
> * This could deliver an interrupt on a dying CPU and crash the
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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