On Tue, Nov 21, 2017 at 10:39 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 3 November 2017 at 00:00, Francisco Iglesias > <frasse.igles...@gmail.com> wrote: >> Hi, >> >> This patch series is an attempt to add support for the ZynqMP QSPI >> (consisting >> of the Generic QSPI and the legacy QSPI) to the xlnx-zcu102 board and connect >> Numonyx n25q512a11 flashes to the QSPI. Also some functionality is added to >> m25p80. >> >> The series starts by adding support in m25p80 for continous read out of >> status >> registers, SST flash READ ID commands, bank address register accesses, bulk >> erase (0x60) and two Numonyx flashes (n25q512a11 and n25q512a13). Thereafter >> it >> updates the striping behaviour to be bit big endiann in the Xilinx QSPI model >> and adds support for RX discard, zero pumping according transfer register >> and 4 >> byte LQSPI addresses. Finally it adds support for the ZynqMP Generic QSPI and >> adds the ZynqMP QSPI to the xlnx-zcu102 board. >> >> Best regards, >> Francisco Iglesias > > Hi; just a note to say that I'm assuming the Xilinx folk are going > to review the xilinx_spips patches in this set...
Yep, we will! Alistair > > thanks > -- PMM >
