On Fri, Nov 17, 2017 at 4:46 PM, Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> wrote: > On 17/11/17 14:53, Artyom Tarasenko wrote: > >> On Fri, Nov 17, 2017 at 2:42 PM, Mark Cave-Ayland >> <mark.cave-ayl...@ilande.co.uk> wrote: >>> Since the EBus is effectively a PCI-ISA bridge then the underlying ISA bus >>> should be contained within the PCI bridge itself. >> >> While it's like that on the Sabre chipset, the Spitfire chipset (which >> I hope to add at some point) has the EBus, but no PCI, so maybe it's >> better to model it separately. >> On the other hand, the Spitfire has different EBus devices >> (particularly different type of the serial ports), so I'm not sure. > > Oh I didn't realise you had more plans in this area :) Any idea when > you'll be able to work on the them?
After I make AIX boot. :-) > TBH as you probably already know, > even the patchset in its current form with the ISA bus encapsulation is > so much better than what is already there, so I'd prefer to merge it and > help you work through any problems later unless you feel particularly > strongly? Ok, let's do it. Reviewed-by: Artyom Tarasenko <atar4q...@gmail.com> -- Regards, Artyom Tarasenko SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
