On Fri, 10 Nov 2017 17:40:12 +0800 Yi Min Zhao <zyi...@linux.vnet.ibm.com> wrote:
> 在 2017/11/10 上午3:23, Cornelia Huck 写道: > > On Tue, 7 Nov 2017 18:24:38 +0100 > > Pierre Morel <pmo...@linux.vnet.ibm.com> wrote: > > > >> Let's move the memory region write from pcistg into a dedicated > >> function. > >> This allows us to prepare a later patch searching for subregions > >> inside of the memory region. > > OK, so here is the memory region write. Do we have any sleeping > > endianness bugs in there for when we wire up tcg? I'm not sure how this > > plays with the bswaps (see patch 1). > > > > But maybe I've just gotten lost somewhere. > I think there's no error. For PCI bars' MRs, we got the little-endian data > that is exactly fit to the byte ordering of pcilg instruction. For PCI > config > space, the data has been swapped according to the cpu byte ordering. Host or target cpu? > So we use zpci_swap_endian() to swap the data back to the little-endian > ordering. That swap is unconditional. If we were running on a little-endian host, it would be wrong, wouldn't it? > > > >> Signed-off-by: Pierre Morel <pmo...@linux.vnet.ibm.com> > >> Reviewed-by: Yi Min Zhao <zyi...@linux.vnet.ibm.com> > >> --- > >> hw/s390x/s390-pci-inst.c | 27 +++++++++++++++++---------- > >> 1 file changed, 17 insertions(+), 10 deletions(-)
